$1.00 The output of an OR gate is connected directly to the input of an AND gate
The output of an OR gate is connected directly to the input of an AND gate. The other AND gate input is a constant "Enable" HIGH. A technician checks the inputs to the OR gate and notes a HIGH and LOW. The output of the OR gate is noted as being a HIGH. The "Enable" HIGH input to the AND gate is verified as normal. The technician checks the OR gate input to the AND gate and observes a LOW or no voltage condition. Assuming CMOS gates, what is the most probable cause?
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- Posted on Mar. 19, 2010 at 08:01:02AM
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